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| om .c 4U et he Features aS at .D w w w * * * * * * * * * * * * * * Programmable Serial Interface PRELIMINARY (High Speed Devices) Programmable Bandwidth * Power-saving mode * Up to two serial channels available to allow: -- High-Bandwidth -- Redundancy * Supported standards: -- InfiniBandTM -- SONET OC-48 200 Mbps - 1.5 Gbps, 2.5 Gbps serial signaling rate Flexible parallel-to-serial conversion in transmit path Flexible serial-to-parallel conversion in receive path Multiple selectable loopback/loop-through modes 100K to 200K usable gates of CPLD logic 240K to 480 Kb of integrated memory -- 192K to 384Kb of synchronous or asynchronous SRAM * * -- 48K to 96Kb of true Dual-Port or FIFO RAM Internal transmit and receive PLLs Logic dedicated Spread Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial input with internal termination and DC-restoration Differential CML serial output with source matched impedance of 50 160-240 user programmable I/Os Any VoltTM I/O interface -- Programmable as 1.8V, 2.5V, 3.3V Multiple I/O standards -- LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), and GTL+ Direct interface to standard fiber-optic modules Designed to drive: -- Fiberoptic Modules -- Copper Cables -- Circuit Board Traces -- Backplane Links -- Box-to-Box Links -- Chip-to-Chip Communication * Extremely flexible clocking options -- Four global clocks -- Up to 192 additional product term clocks * * * * -- Clock polarity at every register Carry chain logic for fast and efficient arithmetic operations Fully PCI compliant (Rev. 2.2) JTAG programming interface with boundary scan support High-Speed (HS) or Frequency Agile (FA) Programmable Serial InterfaceTM (PSITM) versions available m o .c U t4 e e h S ta a .D w w w Frequency Agile PSI Features[1] -- COMMA or Full K28.5 detect * * * * -- Digital signal detect -- Frequency range detect * Supported standards: -- Fibre Channel -- Gigabit Ethernet -- ESCON -- DVB -- SMPTE * 200 Mbps-1.5 Gbps serial signaling rate per channel * Up to eight serial channels available to allow: -- Frequency Agile -- Redundancy * Selectable input and output clocking options * MultiFrameTM receive framer provides alignment to: -- Bit, byte, half-word, word, multi-word -- Single or Multi-byte framer for byte alignment -- Low-latency option Skew alignment support for multiple bytes of offset Selectable parity check/generate Serial Built-In-Self-Test (BIST) for at-speed link testing Per-channel Link Quality Indicator -- Analog signal detect Development Software * Warp(R) -- IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing -- Active-HDL FSM graphical finite state machine editor -- Active-HDL SIM post-synthesis timing simulator -- Static Timing Analyzer for critical path analysis High-Speed PSI Features * 2.5 Gbps/channel serial signaling rate * Full Bellcore and ITU jitter compliance Note: 1. For more detail, refer to the "Frequency Agile PSI" data sheet. -- Architecture Explorer for detailed design analysis -- Available on Windows(R) 95, 98 & NT for $99 -- Supports all Cypress programmable logic products Cypress Semiconductor Corporation Document #: 38-02021 Rev. *B * 3901 North First Street * San Jose om .c 4U et he aS at .D w w w * CA 95134 * 408-943-2600 Revised August 31, 2001 Programmable Serial Interface (High Speed Devices) PRELIMINARY PSI Quick Reference Selection Guide High-Speed/SONET/SDH PSI Serial Bandwidth Logic Gate Density 100K 200K 1 x 2.5 Gbps 25G01K100 2 x 2.5 Gbps 25G02K100 25G02K200 Frequency-Agile PSI Serial Bandwidth 4 x 0.2 - 1.5 Gbps 15G04K100 15G04K200 15G08K200 8 x 0.2 - 1.5 Gbps PSI Family Standards Supported PSI Device SONET/SDH CYS25G01K100 CYS25G02K100 CYS25G02K200 High Speed CYP25G01K100 CYP25G02K100 CYP25G02K200 Frequency Agile CYP15G04K100 CYP15G04K200 CYP15G08K200 SONET/SDH (OC48/STM16) X X X X X X X X X X X X X X X X X X InfiniBand Fibre Channel Gigabit Ethernet ESCON SMPTE 259/292 Custom X X X X X X X X X PSI Family General Selection Guide Device 25G01K100 25G02K100 25G02K200 15G04K100 15G04K200 15G08K200 Typical Gates 46K-144K 46K-144K 92K-288K 46K-144K 92K-288K 92K-288K Macrocells 1536 1536 3072 1536 3072 3072 Cluster memory (Kbits) 192 192 384 192 384 384 Channel memory (Kbits) 48 48 96 48 96 96 Maximum User Programmable I/O 240 194 320 206 332 206 Package Offering 456-BGA (35x35 mm, 1.27 mm pitch) 456-BGA (35x35 mm, 1.27 mm pitch) 700-BGA (45x45 mm, 1.27 mm pitch) 456-BGA (35x35mm, 1.27 mm pitch) 700-BGA (45x45 mm, 1.27 mm pitch) 700 BGA (45x45 mm, 1.27 mm pitch) Shaded areas contain advance information. PSI Family Performance Selection Guide Device 25G01K100 25G02K100 25G02K200 15G04K100 15G04K200 15G08K200 Channels & Link Speed 1 x 2.5 Gbps 2 x 2.5 Gbps 2 x 2.5 Gbps 4 x 0.2 - 1.5 Gbps 4 x 0.2 - 1.5 Gbps 8 x 0.2 - 1.5 Gbps Total Bandwidth 2.5 Gbps 5.0 Gbps 5.0 Gbps 6.0 Gbps 6.0 Gbps 12.0 Gbps fMAX2 (MHz) 222 222 181 222 181 181 Logic Speed-- tPD Pin-to-Pin (ns) 7.5 7.5 8.5 7.5 8.5 8.5 Standby ICC[2] 16 mA 22 mA 22 mA 18 mA 18 mA 26 mA Note: 2. Standby ICC values are with logic PLL not utilized, no output load, and stable inputs. 3. Shaded area is preliminary Document #: 38-02021 Rev. *B Page 2 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY GCLK[1:0] GCTL[3:0] 2 GCLK[1:0] 2 4 PLL & Clock MUX I/O Bank 2 2 I/O Bank 2 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0] 2 2 2 2 I/O Bank LB 0 LB 1 LB 7 LB 6 LB 1 LB 2 LB 3 Cluster RAM LB 6 LB 1 LB 6 LB 1 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0] 2 2 2 2 I/O Bank LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM Phase Align Buffer Deserializer Phase Align Buffer Deserializer Serializer Serializer TX RX TX RX Serial Signal Bank Figure 1. High-Speed PSITM Block Diagram (25G02K100) with I/O Bank Structure. Document #: 38-02021 Rev. *B Page 3 of 58 XCVR CNTRL & I/O I/O Bank I/O Bank LB 0 LB 7 LB 0 LB 7 LB 0 LB 7 Programmable Serial Interface (High Speed Devices) PRELIMINARY GCLK[1:0] PLL & Clock MUX GCTL[3:0] 2 4 GCLK[1:0] 2 I/O Bank 2 2 I/O Bank 2 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0] 2 2 2 2 I/O Bank LB 1 LB 2 LB 3 Cluster RAM LB 6 LB 1 LB 6 LB 1 LB 6 LB 1 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0] 2 2 2 2 I/O Bank LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM Phase Align Buffer Deserializer Serializer TX RX Serial Signal Bank Figure 2. High-Speed PSITM Block Diagram (25G01K100) with I/O Bank Structure. Document #: 38-02021 Rev. *B Page 4 of 58 XCVR CNTRL & I/O I/O Bank I/O Bank LB 0 LB 7 LB 0 LB 7 LB 0 LB 7 LB 0 LB 7 Programmable Serial Interface (High Speed Devices) PRELIMINARY Functional Description The Programmable Serial Interface (PSI) family is a point-topoint or point-to-multipoint programmable communications building block allowing the manipulation and transfer of data over high-speed serial links at signaling speeds ranging from 200 Mbps to 1.5Gbps or 2.5 Gbps per serial link. The PSI family is designed to combine the high speed, predictable timing, high density, low power, and ease of use of complex programmable logic devices (CPLD) with the serializing/deserializing (SERDES) capability of high-speed serial transceivers. The family is divided into two groups: High-Speed PSI and Frequency--Agile PSI. Both groups have unique transceiver characteristics that define the specific transceiver block operation of a given PSI device. The architecture of the device is based on logic block clusters (LBC) and serial transceiver blocks that are connected by horizontal and vertical routing channels. Each LBC features eight individual logic blocks (LB) of 16 marcrocells and two cluster memory blocks. Adjacent to each LBC is a channel memory block which is externally accessible through the I/O interface. Each transmit channel of the transceiver accepts parallel characters, encodes each character for transport and converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decoding the data into characters and presents these characters to the routing channels of the PSI unit. High-Speed PSI The transceiver operation of the high-speed programmable serial interface devices is self-contained in a single block. It has separate transmit and receive PLLs and a Clock and Data Recovery (CDR) unit for flexible clocking. The transmit channel accepts a 16-bit input character from the routing channels and passes the character to an elasticity buffer. This character is then serialized and output on dual differential transmissionline drivers at the required bit-rate. The receive channel accepts a serial bit-stream from the two differential line receivers. This bit-stream is deserialized and a 16-bit character is presented to the routing channels in the PSI device. The block also features loop-back and loop-through modes for simplified design debugging. Global Routing Description The routing architecture in the PLD block of a PSI device is made up of horizontal and vertical (H&V) routing channels. These routing channels allow signals to move among I/Os, logic blocks and memories. In addition to the horizontal and vertical routing channels that interconnect the I/O banks, channel memory blocks, transceiver blocks and logic block clusters, each LBC contains a Programmable Interconnect MatrixTM (PIMTM), which is used to route signals among the logic blocks and the cluster memory blocks in the LBC. Figure 5 is a block diagram of the routing channels that interface within the PSI architecture. The LBC is exactly the same for every member of the PSI family. Transceiver Block Each transceiver block of a given PSI device will have one serializer transmit path and one deserializer receive path operating at a speed from 200 Mbps to 1.5Gbps or 2.5 Gbps. The transceiver block interfaces to the routing channels of the PSI device through highly configurable datapath cells. For specific architecture and operation of the transceiver blocks please refer to the Serial Transceiver Operation section (page 17). High-Speed PSI Transceiver Blocks High-Speed PSI devices include one or two transceiver blocks operating at 2.5 Gbps per channel. Both channels operate independently of each other. They use the same reference clock. The internal interfacing to the transceiver blocks of the highspeed device occur through the port definition of the highspeed transceiver block. The internal signals and their definition are described in the "Pin & Signal Description" section (page 46). Standard Datapath Cell Figure 4 is a block diagram of the PSI datapath cell. The datapath cell contains a three-state transmit buffer, a receive buffer, and a register that can be configured as an transmit or receive register. The Transceiver Enable (TE) can be selected from one of the four global control signals or from one of two Output Control Channel (OCC) signals. The transmit enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes VCC and GND as inputs. One of the global clocks can be selected as the clock for the datapath cell register. The clock mux output is an input to a clock polarity mux that allows the transmit/receive register to be clocked on either edge of the clock. CY PSI + REFCLK - System Bus Programmable Host Bus Interface Optical Transceiver RD+ RD- SD TD- TD+ Optical Fiber Links IN+ IN- SD OUT- OUT+ Serial Data Serial Data Figure 3. High-Speed PSI System Connections with an Optical Interface. Document #: 38-02021 Rev. *B Page 5 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Registered TE Mux TE Mux D From Output PIM Receive Mux 3 C RES Q C To Routing Channel Output Control Channel OCC Global Control Signals Global Clock Signals Register Receive Mux C C Transmit Mux Register Enable Mux Clock Polarity Mux C D E Q C RES Signal 3 Clock Mux 2 C C Register Reset Mux 3 C Figure 4. Block Diagram of a Standard Datapath Cell. Logic Block Cluster (LBC) The PSI architecture consists of several logic block clusters, each of which have 8 Logic Blocks (LB) and 2 cluster memory blocks connected via a Programmable Interconnect Matrix (PIM) as shown in Figure 6. Each cluster memory block consists of 8-Kbit single-port RAM, which is configurable as synchronous or asynchronous. The cluster memory blocks can be cascaded with other cluster memory blocks within the same LBC as well as other LBCs to implement larger memory functions. If a cluster memory block is not specifically utilized by the designer, Cypress's Warp software can automatically use it to implement large blocks of logic. All LBCs interface with each other via horizontal and vertical routing channels. I/O Block LB LB LB LB Cluster Memory Block LB 72 LB Cluster PIM 64 LB LB Cluster Memory Block Channel Memory Block Channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels 72 I/O Block 64 H-to-V PIM V-to-H PIM Pin inputs from the I/O cells drive dedicated tracks in the horizontal and vertical routing channels Figure 5. PSI Routing Interface. Document #: 38-02021 Rev. *B Page 6 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Clock Inputs GCLK[3:0] 4 Logic Block 0 CC 36 16 36 16 Logic Block 7 CC Logic Block 1 CC 36 16 36 16 Logic Block 6 CC Logic Block 2 CC 36 16 PIM 36 16 Logic Block 5 CC Logic Block 3 36 16 36 16 Logic Block 4 Cluster Memory 0 25 8 25 8 Cluster Memory 1 CC = Carry Chain 64 Inputs From Horizontal Routing Channel 64 Inputs From Vertical Routing Channel 144 Outputs to Horizontal and Vertical cluster-to-channel PIMs Figure 6. PSI Logic Block Cluster Diagram. Logic Block (LB) The logic block is the basic building block of the PSI architecture. It consists of a product term array, an intelligent productterm allocator, and 16 macrocells. Product Term Array Each logic block features a 72 x 83 programmable product term array. This array accepts 36 inputs from the PIM. These inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 83 product terms in the array can be created from any of the 72 inputs. Of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. The final product term is the Product Term clock (PTCLK) and is shared by all 16 macrocells within a logic block. Product Term Allocator Through the product term allocator, Warp software automatically distributes the 80 product terms as needed among the 16 macrocells in the logic block. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On PSI devices, product terms are steered on an individual basis. Any number between 1and 16 product terms can be steered to any macrocell. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only created once. The PSI product term allocator allows sharing across groups of four macrocells in a variable fashion. The software automatically takes advantage of this capability so that the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All steering and sharing configurations have been incorporated in the timing specifications for the PSI devices. . Document #: 38-02021 Rev. *B Page 7 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Macrocell Within each logic block there are 16 macrocells. Each macrocell accepts a sum of up to 16 product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial mode. Figure 7 displays the block diagram of the macrocell. The register can be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be preset or reset based on an AND expression or an OR expression. An XOR gate in the PSI macrocell allows for many different types of equations to be realized. It can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the D flip-flop into a T flip-flop. The carry-chain input mux allows additional flexibility for the implementation of different types of logic. The macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even generic XOR logic. The output of the macrocell is either registered or combinatorial. Carry Chain Logic The PSI macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic operations. The carry logic connects macrocells in up to 4 logic blocks for a total of 64 macrocells. Effective data path operations are imCarry In (from macrocell n-1) 0 1 C plemented through the use of carry-in arithmetic, which drives through the circuit quickly. Figure 7 shows that the carry chain logic within the macrocell consists of two product terms (CPT0 and CPT1) from the PTA and an input carry-in for carry logic. The inputs to the carry chain mux are connected directly to the product terms in the PTA. The output of the carry chain mux generates the carry-out for the next macrocell in the logic block as well as the local carry input that is connected to an input of the XOR input mux. Carry-in and a configuration bit are inputs to an AND gate. This AND gate provides a method of segmenting the carry chain in any macrocell in the logic block. Macrocell Clocks Clocking of the register is highly flexible. Four global synchronous clocks (GCLK[3:0]) and a Product Term clock (PTCLK) are available at each macrocell register. Furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell diagram in Figure 7). PRESET/RESET Configurations The macrocell register can be asynchronously preset and reset using the PRESET and RESET mux. Both signals are active high and can be controlled by either of two Preset/Reset product terms (PRC[1:0] in Figure 7) or GND. In situations where the PRESET and RESET are active at the same time, RESET takes priority over PRESET. PRESET Mux Carry Chain Mux CPT0 CPT1 C XOR Input Mux 3 C Output Mux 2 C PSET To PIM FROM PTM Up To 16 PTs Clock Mux GCLK[3:0] PTCLK 3 C C Clock Polarity Mux D Q C RES Q PRC[1:0] 0 1 Carry Out (to macrocell n+1) 3 C RESET Mux Figure 7. PSI Macrocell. Document #: 38-02021 Rev. *B Page 8 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Embedded Memory Each member of the PSI family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), or synchronous FIFO memory. The memory organization is configurable as 4Kx1, 2Kx2, 1Kx4 and 512x8. The second type of memory block is located within each LBC and is referred to as a cluster memory block. Each LBC contains two cluster memory blocks that are 8192 bits in size. Similar to the channel memory blocks, the cluster memory blocks can be configured as 8Kx1, 4Kx2, 2Kx4 and 1Kx8 and can be configured as either asynchronous or synchronous Single-Port RAM or ROM. Cluster Memory Each logic block cluster of the PSI device contains two 8192bit cluster memory blocks. Figure 8 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster PIM. The output of the cluster memory block can be optionally registered to perform synchronous pipelining or to register asynchronous read and write operations. The output registers contain an asynchronous RESET which can be used in any type of sequential logic circuits (e.g., state machines). There are four global clocks (GCLK[3:0]) and one local clock available for the input and the output registers. The local clock for the input registers is independent of the one used for the output registers. The local clock is generated in the user-design in a macrocell or comes from an I/O pin. Cluster Memory Initialization The cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use of look-up-table (LUT) logic and ROM applications, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory The PSI architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. The channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous Single-Port RAM, Dual-Port RAM, ROM, or synchronous FIFO memory. Data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. All data and FIFO logic outputs drive dedicated tracks in the horizontal and vertical routing channels. The clocks for the channel memory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. The clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. Dual-Port (Channel Memory) Configuration Each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. The inputs to the Dual-Port memory are driven from the horizontal and vertical routing channels. The data outputs drive dedicated tracks in the routing channels. The interface to the routing is such that Port A of the Dual-Port interfaces primarily with the horizontal routing channel and Port B interfaces primarily with the vertical routing channel. . DIN[7:0] D Q C 3 Write Control Logic 2 C 8 ADDR[12:0] D Q C Row Decode (1024 Rows) WE D Q Write Pulse C 10 Cluster PIM GCLK[3:0] Local CLK 5:1 3 C C 3 1024x8 Asynchronous SRAM 8 DOUT[7:0] Q C D R Read Control Logic 2 C RESET GCLK[3:0] Local CLK 5:1 3 C C Figure 8. Block Diagram of Cluster Memory Block. Document #: 38-02021 Rev. *B Page 9 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs of the dual-port memory can also be registered. Clocks for the output registers are also selected from four global clocks and two local clocks. One clock polarity mux per port allows the use of true or complement polarity for input and output clocking purposes. Arbitration The Dual-Port configuration of the Channel Memory Block provides arbitration when both ports access the same address at the same time. Depending on the memory operation being attempted, one port always gets priority. See Table 1 for details on which port gets priority for read and write operations. An active-LOW `Address Match' signal is generated when an address collision occurs. Table 1. Arbitration Result: Address Match Signal Becomes Active Result of Port A Port B Arbitration Read Write Read Read No arbitration required Port A gets priority Comment Both ports read at the same time If Port B requests first then it will read the current data. The output will then change to the newly written data by Port A If Port A requests first then it will read the current data. The output will then change to the newly written data by Port B Port B is blocked until Port A is finished writing horizontal and vertical routing channels. This allows the FIFO blocks to be expanded by using multiple FIFO blocks on the same horizontal or vertical routing channel without any speed penalty. In FIFO mode, the write and read ports are controlled by separate clock and enable signals. The clocks for each port are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs from the read port of the FIFO can also be registered. One clock polarity mux per port allows using true or complement polarity for read and write operations. The write operation is controlled by the clock and the write enable pin. The read operation is controlled by the clock and the read enable pin. The enable pins can be sourced from horizontal or vertical channels. Channel Memory Initialization The channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use LUT logic and ROM applications, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory Routing Interface Similar to LBC outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in Figure 9. This allows the channel memory blocks to be expanded easily. These dedicated lines can be routed to I/O pins as chip outputs or to other logic block clusters to be used in logic equations. All channel memory inputs are driven from the routing channels Read Write Port B gets priority Write Write Port A gets priority FIFO (Channel Memory) Configuration The channel memory blocks are also configurable as synchronous FIFO RAM. In the FIFO mode of operation, the channel memory block supports all normal FIFO operations without the use of any general-purpose logic resources in the device. The FIFO block contains all of the necessary FIFO flag logic, including the read and write address pointers. The FIFO flags include an empty/full flag (EF), half-full flag (HF), and programmable almost-empty/full (PAEF) flag output. The FIFO configuration has the ability to perform simultaneous read and write operations using two separate clocks. These clocks may be tied together for a single operation or may run independently for asynchronous read/write (w.r.t. each other) applications. The data and control inputs to the FIFO block are driven from the horizontal or vertical routing channels. The data and flag outputs are driven onto dedicated routing tracks in both the 4096-bit Dual Port Array Configurable as Async/Sync Dual Port or Sync FIFO Configurable as 4Kx1, 2Kx2, 1Kx4 and 512x8 block sizes Global Clock Signals GCLK[3:0] Vertical Channel All channel memory outputs drive dedicated tracks in the routing channels Horizontal Channel Figure 9. Block Diagram of Channel Memory Block. Document #: 38-02021 Rev. *B Page 10 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY I/O Banks The PSI interfaces the horizontal and vertical routing channels to the pins through I/O banks. There are several I/O banks per device as shown in Figure 10 and all I/Os from an I/O bank are located in the same section of a package for PCB layout convenience. There exist two kinds of I/O banks; fixed-signal I/O banks and user programmable I/O banks. The first fixed signal bank is the Serial Signal Bank. This bank includes all differential serial data transmission and receive signals. The second bank is the Transceiver Control Bank. This bank includes all static signal pins required for the configuration and operation of the transceiver blocks in each of the PSI devices. Each PSI device has several types of user programmable I/O banks. The table on the following page indicates the availability of each type of programmable bank by device. Supported I/O standards for each bank are addressed by the appropriate VREF and VCCIO voltages. All the VREF and VCCIO pins in an I/O bank must be connected to the same VREF and VCCIO voltage respectively. This requirement restricts the number of I/O standards supported by an I/O bank at any given time. It also dictates the I/O standard used for the GCTL[3:0] pins. The architecture defining each programmable I/O bank consists of several I/O cells, where each I/O cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. Each I/O cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. There are four dedicated inputs (GCTL[3:0]) that are used as Global Control Signals available to every I/O cell. These global control signals may be used as output enables, register resets and register clock enables as shown in Figure 11. PSI Programmable I/O Banks Device Flexible SemiFlexible Specific VCCIO VREF 25G01K100 Bank[0:3, 5] 25G02K100 Bank[0:3] Bank[6:7] Bank[4] VCCIO=3.3V 1.5V 0.68-0.90V Bank[5:7] Bank[4] VCCIO=3.3V 1.5V 0.68-0.90V IO Standards I/O Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV 0.9 1.3 1.3 1.15 1.15 0.68 0.68 0.68 0.68 1.1 1.7 1.7 1.35 1.35 0.9 0.9 0.9 0.9 VREF (V) Min N/A Max 3.3 V 3.3 V 3.0 V 2.5 V 1.8 V 3.3 V N/A 3.3 V 3.3 V 2.5 V 2.5 V 1.5 V 1.5 V 1.5 V 1.5 V N/A N/A N/A N/A N/A N/A 1.5 1.5 1.5 1.25 1.25 0.75 0.75 1.5 1.5 VCCIO Termination Voltage (VTT) I/O Bank I/O Bank I/O Bank I/O Bank I/O Bank Serial Bank XCVR CNTL & I/O PSI I/O Bank I/O Bank I/O Bank Figure 10. PSI I/O Bank Block Diagram. Document #: 38-02021 Rev. *B Page 11 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY . Registered OE Mux OE Mux D From Output PIM Input Mux 3 C RES Q C To Routing Channel Output Control Channel OCC Global Control Signals Global Clock Signals Register Input Mux C C Output Mux Register Enable Mux Clock Polarity Mux C D E Q C RES Bus Hold I/O C 3 Clock Mux Slew Rate Control C 2 C C Register Reset Mux 3 C Figure 11. Block Diagram of I/O Cell. I/O Cell Figure 11 is a block diagram of the PSI I/O cell. The I/O cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. The output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. The input of the device and the pin output can each be configured as registered or combinatorial, however only one path can be configured as registered in a given design. The output enable can be selected from one of the four global control signals or from one of two Output Control Channel (OCC) signals. The output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes VCC and GND as inputs. One of the global clocks can be selected as the clock for the I/O cell register. The clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock. Slew Rate Control The output buffer has a slew rate control option. This allows the ouput buffer to slew at a fast rate (3 V/ns) or a slow rate (1 V/ns). All I/Os default to fast slew rate. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. Programmable Bus Hold On each I/O pin, user-programmable bus-hold is included. Bus-hold, which is an improved version of the popular internal Document #: 38-02021 Rev. *B Device 25G01K100 25G02K100 pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note "Understanding Bus-Hold - A Feature of Cypress CPLDs." Clocks PSI has four primary global clock trees in the CPLD portion of the device (INTCLK[3:0]). Each of these clock trees distributes a clock signal to every cluster, channel memory, and I/O cell in the CPLD. The global clock trees are designed such that the clock skew is minimized while maintaining an acceptable clock delay. Each of the INTCLKs can choose from two input sources for the clock signal: A PLL derived output or another one as shown in the table below: INININTCLK[0] TCLK[1] TCLK[2] GCLK[0] GCLK[0] GCLK[1] RXCLK TXCLK TXCLK INTCLK[3] RXCLK RXCLK_B GCLK[0] and GCLK[1] are accessible through pins on the device package. TXCLK and RXCLK are provided internally to the device. TXCLK (transmit clock) is intended for data transfer from the CPLD block to the transmit channel of the transceiver block. RXCLK (receive clock) is intended for data transfer from the receive channel of the transceiver block to the CPLD block. The TXCLK and RXCLK can also be used for Page 12 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY logic inside the CPLD block, e.g., for data processing. RXCLK_B is the RXCLK for the second transceiver block. Clock Tree Distribution The global clock tree performs two primary functions. First, the clock tree generates the four internal global clocks by multiplexing four reference clocks derived from the Transceiver Blocks and from the package pins and four PLL driven clocks. Second, the clock tree distributes the four global clocks to every cluster, channel memory, I/O block, and datapath cell on the die. The global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. Spread AwareTM PLL Each device in the PSI family features an on-chip PLL designed using Spread AwareTM technology for low EMI applications. In general, PLLs are used to implement time-divisionmultiplex circuits to achieve higher performance with fewer device resources. For example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit circuitry that runs internally at 80 MHz. PLLs can also be used to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. There are several frequency multiply (X1, X2, X4, X8) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (GCLK[0]). For increased flexibility, there are seven phase shifting options which allow clock skew/deskew by 45, 90, 135, 180, 225, 270 or 315. The Spread Aware feature refers to the ability of the PLL to track a spread-spectrum input clock such that its spread is seen on the output clock with the PLL staying locked. The total amount of spread on the input clock should be limited to 0.6% of the fundamental frequency. Spread Aware feature is supported only with X1, X2 and X4 multiply options. The Voltage Controlled Oscillator (VCO), the core of the PSI PLL is designed to operate within the frequency range of 100 MHz to 266 MHz. Hence, the multiply option combined with input (GCLK[0]) frequency should be selected such that this VCO operating frequency requirement is met. This is demonstrated in Table 2 (columns 1, 2, and 3). Another feature of this PLL is the ability to drive the output clock (INTCLK) off the PSI chip to clock other devices on the board, as shown in Figure 12 below. This off-chip clock is half the frequency of the output clock as it has to go through a register (I/O register or a macrocell register). This PLL can also be used for board deskewing purpose by driving a PLL output clock off-chip, routing it to the other devices on the board and feeding it back to the PLL's external feedback input (GCLK[1]). When this feature is used, only limited multiply, divide and phase shift options can be used. Table 2 describes the valid multiply and divide options that can be used without an external feedback. Table 3 describes the valid multiply and divide options that can be used with an external feedback. off-chip signal (external feedback) INTCLK0, INTCLK1, INTCLK2, INTCLK3 Any Register Send a global clock off chip GCLK1 Normal I/O signal path Lock Detect/IO pin Clock Tree Delay 2 C Phase selection C Divide 1-6,8,16 INTCLK0 GCLK0 / fb fb Lock Phase selection 2 C / Clk 00 Clk 450 Clk 900 Divide 1-6,8,16 INTCLK1 GCLK1 GCLK0 Source Clock Phase selection 2 C Clk 1350 Clk 1800 Clk 2250 Clk 2700 / Divide 1-6,8,16 INTCLK2 TXCLK 2 Clk 3150 PLL X1, X2, X4, X8 Phase selection C Divide 1-6,8,16 INTCLK3 RXCLK 2 / GCLK[1:0] C Figure 12. Block Diagram of Spread Aware PLL for CYP25G01K100. Document #: 38-02021 Rev. *B Page 13 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY INTCLK0, INTCLK1, INTCLK2, INTCLK3 Any Register Send a global clock off chip INTCLK1 Normal I/O signal path Lock Detect/IO pin Clock Tree Delay 2 C Phase selection C Divide 1-6,8,16 INTCLK0 GCLK0 / fb fb Lock Phase selection 2 C / Clk 0 0 Divide 1-6,8,16 INTCLK1 RXCLK Clk 450 Clk 900 Source Clock Phase selection 2 C Clk 1350 Clk 1800 Clk 2250 Clk 2700 Clk 3150 / Divide 1-6,8,16 INTCLK2 TXCLK 2 PLL X1, X2, X4, X8 Phase selection C Divide 1-6,8,16 INTCLK3 RXCLK_B 2 / GCLK[0] C Figure 13. Block Diagram of Spread Aware PLL for CYP25G02K100. Table 2. PLL Multiply and Divide Options--without INTCLK1 Feedback Input Frequency (GCLK[0]) fPLLI (MHz) 12.5-25 25-33 33-50 50-66 66-100 100-133 Valid Multiply Options Value 8 8 4 4 4 2 2 2 1 VCO Output Frequency (MHz) 100-200 200-266 100-133 133-200 200-266 100-133 133-200 200-266 100-133 Value 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) 6.25-200 12.5-266 6.25-133 8.33-200 12.5-266 6.25-133 8.3-200 12.5-266 6.25-133 Off-Chip Clock Frequency 3.12-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66 Table 3. PLL Multiply and Divide Options--with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-66 66-100 100-133 Value 1 1 1 VCO Output Frequency (MHz) 100-133 133-200 200-266 Value 1 1 1 Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-133 133-200 200-266 Off-Chip Clock Frequency 50-66 66-100 100-133 Document #: 38-02021 Rev. *B Page 14 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Table 4 describes the valid phase shift options that can be used with or without an external feedback. Table 4. PLL Phase Shift Options-- with and without INTCLK1 Feedback Without External Feedback 0,45, 90, 135, 180, 225, 270, 315 With External Feedback 0 Table 5 is an example of the effect of all the available divide and phase shift options on a VCO output of 250 MHz. It also shows the effect of division on the duty cycle of the resultant clock. Note that the duty cycle is 50-50 when a VCO output is divided by an even number. Also note that the phase shift applies to VCO output and not to the divided output For more details on the architecture and operation of this PLL please refer to the application note entitled "PSI PLL and Clock Tree." Table 5. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz Divide Factor 1 2 3 4 5 6 8 16 Period (ns) 4 8 12 16 20 24 32 64 Duty Cycle% 40-60 50 33-67 50 40-60 50 50 50 0 (ns) 0 0 0 0 0 0 0 0 45 (ns) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 90 (ns) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 135 (ns) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 180 (ns) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 225 (ns) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 270 (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 315 (ns) 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 Document #: 38-02021 Rev. *B Page 15 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Timing Model One important feature of the PSI family is the simplicity of its timing. All combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the AC specs section) as long as data is routed through the same horizontal and vertical channels. Figure 14 illustrates the true timing model for the 200-MHz devices. For synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate Logic Blocks within the same cluster, as well as separate Logic Blocks within different clusters. This is shown as tSCS and tSCS2 in Figure 14. For combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst-case delay in the 100K gate PSI regardless of the amount of logic or which horizontal and vertical channels are used. This is the tPD shown in Figure 14. For synchronous systems, the input set-up time to the output macrocell register and the clock to output time are shown as the parameters tMCS and tMCCO shown in the Figure 14. These measurements are for any output and synchronous clock, regardless of the logic placement. PSI features: * no dedicated vs. I/O pin delays * no penalty for using 0-16 product terms * no added delay for steering product terms * no added delay for sharing product terms * no output bypass delays The simple timing model of the PSI family eliminates unexpected performance penalties. tSCS GCLK[3:0] 4 4 4 4 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 8 Kb SRAM RAM tMCS LB 3 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 8 Kb SRAM GCLK[3:0] 4 4 4 4 tSCS2 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM RAM tPD LB 3 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM GCLK[3:0] 4 4 4 4 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM tMCCO Figure 14. Timing Model for 100K gate PSI Devices. Document #: 38-02021 Rev. *B Page 16 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Serial Transceiver Operation The PSI transceiver block is a highly configurable transceiver designed to support reliable transfer of large quantities of data, using high-speed serial links, from one or multiple sources to one or multiple destinations. This block supports either a single 16-bit wide channel in the case of High-Speed PSI devices or four single-byte or single-character channels, that may be combined to support transfer of wider buses, in the case of Frequency Agile PSI devices. of standard LVPECL drivers, and are capable of driving ACcoupled optical modules or transmission lines. Receive Data Path Serial Line Receivers A differential line receiver, IN, is available for accepting the input serial data stream. The serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (VDIF > 25 mV, or 50 mV peakto-peak differential), and can be AC-coupled to +3.3V or +5V powered fiber-optic interface modules. The common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Lock to Data Control Line Receiver routed to the clock and data recovery PLL is monitored for *status of signal detect (SD) pin *status of LOCKREF pin *received data stream outside normal frequency range (200 ppm) This status is presented on the LFI (Line Fault Indicator) output signal, which changes asynchronously in the cases when SD or LOCKREF goes from HIGH to LOW. Otherwise, it changes synchronously to the REFCLK. Clock/Data Recovery The extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a Clock/Data Recovery (CDR) block. The clock extraction function is performed by high-performance embedded phase-locked loop (PLL) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. CDR accepts a character-rate (bit-rate / 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit-rate), to improve PLL acquisition time, and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR will attempt to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL will track REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK is required to be within 200 ppm of the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. For systems using multiple or redundant connections, the LFI output can be used to select an alternate data stream. When an LFI indication is detected, PSI logic can toggle selection of the input device. When such a port switch takes place, it is necessary for the PLL to re-acquire lock to the new serial stream. External Filter The CDR circuit uses external capacitors for the PLL filter. A 0.1-F capacitor needs be connected between RXCN1 and Page 17 of 58 High-Speed PSI Transceiver Operation Transmit Data Path Operating Modes The transmit path of the High-Speed PSI supports 16-bit-wide data paths. Phase-Align Buffer Data from the input register is passed to a phase-align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase-align buffer takes place when the FIFO_RST signal is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase relative to TXCLK is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK; i.e. 180. This time shift allows the delay path of the character clock (relative to REFCLK) to change due to operating voltage and temperature while not effecting the desired operation. FIFO_RST is an asynchronous signal. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, the transmit FIFO has either under or overflowed. The FIFO can be externally reset or logically reset by PSI logic to clear the error indication or if no action is taken, the internal clearing mechanism will clear the FIFO in 9 clock cycles. When the FIFO is being reset, the output data is 1010. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a 156.25-MHz external clock at the REFCLK input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies are listed in the High-Speed PSI Transceiver Timing Parameter Values table under "REFCLK Timing Parameters" (see page 33). The REFCLK input is a standard LVPECL input. Serializer The parallel data from the phase-align buffer is passed to the Serializer which converts the parallel data to serial data using the bit-rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word, and is transmitted first on the serial interface. Serial Output Driver The serial interface Output Driver makes use of high-performance differential CML (Current Mode Logic) to provide a source-matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY RXCP1. Similarly a 0.1-F capacitor needs to be connected between RXCN2 and RXCP2. The recommended packages and dielectric material for these capacitors are 0805 X7R or 0603 X7R. Deserializer The CDR circuit extracts bits from the serial data stream and clocks these bits into the Deserializer at the bit-clock rate. The Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface. Loopback/Timing Modes High-Speed PSI supports various loopback modes as described below. Facility Loopback (Line Loopback With Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high-speed serial receive data (IN) is presented to the high-speed transmit output (OUT) after retiming. In Facility Loopback mode, the high-speed receive data (IN) is also converted to parallel data and presented to the low-speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback With Retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (Non-retimed Data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and receive bit-rate clock is used for transmit side shifter. Reset Modes ALL logic circuits in the device can be reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset. Power-down Mode High-Speed PSI transceiver blocks provide a global powerdown signal PWRDN. When LOW, this signal powers down the entire device to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. Document #: 38-02021 Rev. *B Page 18 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY (156.25 MHz) TXCLK TXD[15:0] FIFO_RST 16 FIFO_ERR TXCLK (156.25 MHz) REFCLK (156.25 MHz) RXCLK RXD[15:0] 16 Output Register /16 Shifter Recovered Bit-Clock RX CDR PLL Lock-to-Ref Retimed Data Input Register TX PLL X16 FIFO /16 TX Bit-Clock Shifter LOOPTIME DIAGLOOP LINELOOP LOOPA Lock-to-Data/ Clock Control Logic OUT PWRDN LOCKREF SD LFI RESET IN Figure 15. High Speed-PSI Transceiver Logic Block Diagram. Document #: 38-02021 Rev. *B Page 19 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY IEEE 1149.1 Compliant JTAG Operation The PSI family has an IEEE std 1149.1 JTAG interface for both Boundary Scan and ISR operations. Four dedicated pins are reserved on each device for use by the Test Access Port (TAP). Boundary Scan The PSI family supports Bypass, Sample/Preload, Extest, Intest, Idcode and Usercode boundary scan instructions. The JTAG interface is shown in Figure 16. Frequency Agile devices also allow system level diagnosis of transceiver interface and interconnect. Boundary scan is supported on the LVCMOS signals, inputs and outputs. The highspeed serial inputs are not part of the JTAG test chain. Instruction Register TDI TDO There are multiple configuration options available for issuing the IEEE std 1149.1 JTAG instructions to the PSI. The first method is to use a PC with the C3 ISR programming cable and software. With this method, the ISR pins of the PSI devices in the system are routed to a connector at the edge of the printed circuit board. The C3 ISR programming cable is then connected between the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on the PSI devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other ISR functions. For more information on the Cypress ISR interface, see the Programming/ISR application notes at http://www.cypress.com/pld/pldappnotes.html. For systems with embedded controllers/processors, a controller/processor may be used to configure the PSI. The PSI ISR software assists in this method by converting the device HEX file into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be configured. The controller/processor then simply directs this ISR stream to the chain of PSI devices to complete the desired reconfiguration or diagnostic operations. Contact your local sales office for information on availability of this option. Programming TMS TCLK JTAG TAP CONTROLLER Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Data Registers Figure 16. JTAG Interface. In-System ReprogrammingTM (ISRTM) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The PSI family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. Configuration The CPLD block in each device of the PSI family is designed with Self-Boot capability. An embedded on-chip EEPROM is used to store configuration data. For PSI devices, programming is defined as the loading of a user's design into the internal EEPROM. Configuration, on the other hand, is defined as the loading of a user's design into the volatile CPLD block. Configuration can begin in two ways. It can be initiated by toggling the Reconfig pin from LOW to HIGH, or by issuing the appropriate IEEE std 1149.1 JTAG instruction to the PSI device via the JTAG interface. There are two IEEE std 1149.1 JTAG instructions that initiate configuration of the PSI. The Self Config instruction causes the PSI to (re)configure with data store in the internal EEPROM. The Load Config instruction causes the PSI to (re)configure with data provided by other sources such as a PC, Automatic Test Equipment (ATE), or an embedded micro-controller/processor via the JTAG port. Document #: 38-02021 Rev. *B The on-chip EEPROM device of the CPLD block is programmed by issuing the appropriate IEEE std 1149.1 JTAG instruction. This can be done automatically using ISR/STAPL software. The configuration bits are sent from a PC through the JTAG port into the PSI via the C3 ISR programming cable. The data is then passed to the internal EEPROM through the NonVolatile (NV) port of the CPLD block. For more information on how to program the PSI through ISR/STAPL, please refer to the ISR/STAPL User Guide. Third-Party Programmers Cypress support is available on a wide variety of third-party programmers. All major programmers (including BP Micro, System General, Hi-Lo) support the PSI family. Development Software Support Warp(R) Warp is a state-of-the-art design environment for designing with Cypress programmable logic. Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware Description Language (HDL) for design entry. Warp accepts VHDL or Verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired Delta39K device. For simulation, Warp provides a graphical waveform simulator as well as VHDL and Verilog Timing Models. VHDL and Verilog are open, powerful, non-proprietary Hardware Description Languages (HDLs) that are standards for behavioral design entry and simulation. HDL allows designers to learn a single language that is useful for all facets of the design process. Third-Party Software Cypress products are supported in a number of third-party design entry and simulation tools. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third party vendors. Page 20 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Soldering Temperature...................................................220C Ambient Temperature with Power Applied............................................... -40C to +85C Junction Temperature....................................................135C VCC relative to Ground Potential...................... -0.5V to 4.2V VCCIO relative to Ground Potential................... -0.5V to 4.6V DC Voltage Applied to Outputs in High Z State -0.5V to 4.5V Range Commercial Output Current into LVCMOS Outputs (LOW)............. 30 mA DC Input voltage......................... ......................-0.5V to 4.5V DC Current into Outputs...................... ................... 20 mA[4] Static Discharge Voltage................................................> 2001V (per MIL-STD-883, Method 3015) Latch-Up Current...........................................................> 200 mA Operating Range Ambient Temperature 0C to +70C VCC VDDQ 3.3V 10% 1.4V to 1.6V Operating Range Range Ambient Temperature 0C to +70C Commercial Junction Temperature 0C to +85C Output Condition 3.3V 2.5V 1.8V 1.5V Notes: 4. DC current into outputs is 36 mA with HSTL III and 48 mA with HSTL IV. VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V VCC 3.3V 0.3V VCCJTAG/ VCCCNFG Same as VCCIO VCCPLL Same as VCC VCEP 3.3V 0.3V Document #: 38-02021 Rev. *B Page 21 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY AC Test Loads and Waveforms to High-Speed PSI Transceiver Block 3.0V Vth=1.4V GND < 1 ns 2.0V 0.8V 3.0V 2.0V 0.8V Vth=1.4V < 1 ns 80% 20% VICLL VICHH 80% 20% 250 ps 250 ps (a) LVTTL Input Test Waveform (b) CML Input Test Waveform VIEHH 80% 20% VIELL 80% 20% 250 ps 250 ps (c) LVPECL Input Test Waveform 3.3V OUTPUT R1=330 R2=510 CL 10 pF (Includes fixture and probe capacitance) R1 CL R2 OUT+ OUT- RL RL =100 (a) TTL AC Test Load (b) CML AC Test Load Document #: 38-02021 Rev. *B Page 22 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Electrical Characteristics Over the Operating Range DC Characteristics VCCIO = 3.3V VCCIO = 2.5V Parameter Description VDRINT VDRIO IIX IOZ IOS[5] IBHL IBHH IBHLO IBHHO Capacitance Parameter CI/O CPCI CCLK CINPECL CSD1 CINC1 Description Input/Output Capacitance PCI compliant I/O Capacitance Clock Signal Capacitance PECL Input Capacitance SD Pin Input Capacitance CML Input Capacitance Test Conditions Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C 5 Min. Max. 10 8 12 4 5 4 Unit pF pF pF pF pF pF Data Retention VCC Voltage (config data may be lost below this) Data Retention VCCIO Voltage (config data may be lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current GND VI 3.6V GND VO VCCIO VCCIO = Max., VOUT = 0.5V VCC = Min., VPIN = VIL VCC = Min., VPIN = VIH VCC = Max. VCC = Max. +40 -40 +250 -250 Test Conditions Min. 1.5 1.2 -10 -10 10 10 -160 +30 -30 +200 -200 Max. Min. 1.5 1.2 -10 -10 10 10 -160 +25 -25 +150 -150 Max. VCCIO = 1.8V Min. 1.5 1.2 -10 -10 10 10 -160 Max. Unit V V A A mA A A A A DC Specifications - Power Parameter ICC2[6] Device 25G01K100 25G02K100 Description Active Power Supply Current Active Power Supply Current Test Conditions Frequency = Max Commercial Frequency = Max Commercial Standby 16 22 Typical 800 1200 Unit mA mA Notes: 5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT=0.5V has been chosen to avoid test problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters. 6. Typical ICC is measured with VCC = 3.3V, TA = 25C, RFEN = LOW, and outputs unloaded. Document #: 38-02021 Rev. *B Page 23 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY DC Characteristics (I/O) Max. Input/ Output Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS1 8 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV 0.9 1.3 1.3 1.1 1.7 1.7 1.8 3.3 Note 7 3.3 3.3 2.5 2.5 1.5 1.5 1.5 1.5 -8 mA -16 mA -7.6 mA -15.2 mA -8 mA -16 mA -8 mA -8 mA VCCIO-1.1V VCCIO-0.9V VCCIO- 0.62V VCCIO-0.43V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VREF (V) Min. VCCIO (V) 3.3 3.3 3.0 2.5 @ IOH = -4 mA -0.1 mA -0.1 mA -0.1 mA -1.0 mA -2.0 mA -0.1 mA - 2 mA -0.5 mA VOH (V) VOH (Min.) 2.4 VCCIO-0.2V VCCIO-0.2V 2.1 2.0 1.7 VCCIO-0.2V VCCIO-0.45V 0.9VCCIO VOL (V) @ IOL = 4 mA 0.1 mA 0.1 mA 0.1 mA 1.0 mA 2.0 mA 0.1 mA 2.0 mA Note 8 8 mA 16 mA 7.6 mA 15.2 mA 8 mA 16 mA 24 mA 48 mA VOL (Max.) 0.4 0.2 0.2 0.2 0.4 0.7 0.2 0.45 0.5VCCIO VREF+0.2 VREF+0.2 VCCIO+0.3 -0.3V VREF+0.2 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V Min. 2.0 -0.3 VCCIO+0.5 -0.5V 0.3VCCIO VREF-0.2 VREF-0.2 VREF-0.2 VREF-0.1 8 VREF-0.1 8 VREF-0.1 VREF-0.1 VREF-0.1 VREF-0.1 Unit V V A A mV mV V V A A V V mV 0.6 0.7 0.5 0.54 0.35 0.4 0.4 0.4 0.4 0.65VCCIO VCCIO+0.3 -0.3V 0.35VCCIO Min. 2.0V 2.0V 2.0V 1.7V VIH (V) Max. Min. VIL (V) Max. 0.8V 0.8V 0.8V 0.7V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V 1.5 mA 0.1VCCIO 1.15 1.35 1.15 1.35 0.68 0.9 0.68 0.9 0.68 0.9 0.68 0.9 Parameter SD Pin LVTTL Inputs VIHT VILT IIHT IILT VINSGLE VDIFFE VIEHH VIELL IIEH IIEL VOHC VOLC VSGLCO Description Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) Output Single-ended Voltage Test Conditions Low = 2.0V, High = VCC + 0.5V Low = -3.0V, High = 0.8V VCC = Max., VIN = VCC VCC = Max., VIN = 0V Max. VCC - 0.3 0.8 50 -50 REFCLK LVPECL Compatible Inputs 200 400 VCC - 1.2 VIN = VIEHH Max. VIN = VIELL Min. 100 differential load 100 differential load 100 differential load -200 VCC - 0.5 VCC - 0.15 VCC - 1.2 280 VCC - 0.7 800 600 1200 VCC - 0.3 750 VCC - 2.0 VCC - 1.45 General Transmitter Differential CML Compatible Outputs (All High-Speed PSI) Notes: 7. See "Power-up Sequence Requirements" for VCCIO requirement. 8. 25 resistor terminated to termination voltage of 1.5V. Document #: 38-02021 Rev. *B Page 24 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Parameter VDIFF IACCM VACCM ZD ZSE ZMSE IDSHORT VDIFFOC VINSGLC VICHH VICLL IICH IICL VRSENSE ZVTT LDR LCMR VRSD VRMAX VDIFFC Description Differential Output AC Common Mode Current AC Common Mode Voltage Differential Output Impedance Single Ended Output Impedance Single Ended Output Impedance Matching Within a Single Lane Short Circuit Current Output Differential Swing Input Single-ended Swing Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Input Sensitivity VTT Impedance Differential Return Loss Common Mode Return Loss Voltage Threshold Maximum Input Voltage (p-p) Input Differential Voltage 50 10 6 20 1.6 1200 VIN = VICHH Max. VIN = VICLL Min. 175 30 1.2 47 20 100 differential load -100 560 25 75 30 Test Conditions 100 differential load Min. 1000 Max. 1600 5 25 125 75 10 100 1500 600 VCC Unit mV A mV % mA mV mV V V A A mV dB dB mV V mV Transmitter Differential CML Compatible Outputs (P25G01K100, P25G02K100 only) Transmitter Differential CML Compatible Outputs (S25G01K100, S25G02K100 only) General Receiver Differential CML Compatible Inputs (All High-Speed PSI) Receiver Differential CML Compatible Inputs (P25G01K100, P25G02K100 only) Receiver Differential CML Compatible Inputs (S25G01K100, S25G02K100 only) Configuration Parameters Parameter tRECONFIG Description Reconfig pin LOW time before it goes HIGH Min. 200 Unit ns Power-up Sequence Requirements * Upon power-up, all the outputs remain three-stated until all the VCC pins have powered-up to the nominal voltage and the part has completed configuration. * The part will not start configuration until VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCEPVCEP have reached nominal voltage. * VCC pins can be powered up in any order. This includes VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCEP. * All VCCIOs on a bank should be tied to the same potential and powered up together. * All VCCIOs (even the unused banks) need to be powered up to at least 1.5V before configuration has completed. * Maximum ramp time for all VCCs should be 0V to nominal voltage in 100 ms. Document #: 38-02021 Rev. *B Page 25 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Characteristics Timing Parameter Values Parameter Combinatorial Mode Parameters tPD tEA tER tPRR tPRO Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster Global control to output enable Global control to output disable Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock Clock to output of an I/O cell register to the output pin associated with that register Macrocell clock to macrocell clock through array logic within the same cluster Macrocell clock to macrocell clock through array logic in different clusters on the same channel I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in Clock to output disable (high-impedance) Clock to output enable (low-impedance) Maximum frequency with internal feedback--within the same cluster Maximum frequency with internal feedback--within different clusters at the opposite ends of a horizontal or vertical channel Set-up time for macrocell used as input register, from input to product term clock Hold time of macrocell used as an input register Product term clock to output delay from input pin Register to register delay through array logic in different clusters on the same channel using a product term clock 6.5 3.0 1.0 8.0 2.0 250 200 4.0 5.0 5.0 5.0 3.5 1.0 1.0 4.0 6.0 10 7.5 ns Description Min. Max. Unit 5.0 5.0 ns ns ns ns 3.6 ns tPRW Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2 3.0 0.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Product Term Clocking Parameters tMCSPT tMCHPT tMCCOPT tSCS2PT ns ns ns ns Note: 9. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa. Document #: 38-02021 Rev. *B Page 26 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Characteristics Timing Parameter Values (continued) Parameter Channel Interconnect Parameters tCHSW tCL2CL Adder for a signal to switch from a horizontal to vertical channel and vice-versa Cluster to Cluster delay adder (through channels and channel PIM) Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array required by a given signal path Adder for carry chain logic per macrocell Maximum cycle to cycle jitter time PLL delay with skew adjustment PLL delay without any skew adjustment Lock time for the PLL Output frequency of the PLL Input frequency of the PLL 6.2 25 1.0 2.0 3.0 ns ns ns Description Min. Max. Unit Miscellaneous Parameters tCPLD tMCCD tMCCJ tDWSA tDWOSA tLOCK fPLLO[10] fPLLI[10] 0.25 0.50 0.35 0.35 3.0 266 133 ns ns ns ns ms MHz MHz PLL Parameters Cluster Memory Timing Parameter Values 200 Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD Cluster memory access time. Delay from address change to read data out Write enable pulse width Address set-up to the beginning of write enable Address hold after the end of write enable with both signals from the same I/O block Data set-up to the end of write enable Data hold after the end of write enable Clock cycle time for flow-through read and write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) Clock cycle time for pipelined read and write operations (from cluster memory input register through the memory to cluster memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data 6.0 2.0 1.0 6.0 0.5 10 11 ns ns ns ns ns ns ns Description Min. Max. Unit Synchronous Mode Parameters tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 5.0 3.0 0.0 11 7.5 ns ns ns ns ns Note: 10. Refer to page 15 and the application note titled "PSI PLL and Clock Tree" for details on the PLL operation & specification. Document #: 38-02021 Rev. *B Page 27 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Cluster Memory Timing Parameter Values (continued) tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 Cluster memory input clock to macrocell clock in the same cluster Cluster memory output clock to macrocell clock in the same cluster Macrocell clock to cluster memory input clock in the same cluster Macrocell clock to cluster memory output clock in the same cluster Asynchronous cluster memory access time from input of cluster to output of cluster 8.0 5.0 4.0 6.5 6.0 ns ns ns ns ns Internal Parameters tCLMCLAA Channel Memory Timing Parameter Values Parameter Dual-Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA Channel memory access time. Delay from address change to read data out Write enable pulse width Address set-up to the beginning of write enable Address hold after the end of write enable with both signals from the same I/O block Data set-up to the end of write enable Data hold after the end of write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) Clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data Channel memory synchronous dual-port address match (busy, clock to data valid) Channel memory input clock to macrocell clock in the same cluster Channel memory output clock to macrocell clock in the same cluster Macrocell clock to channel memory input clock in the same cluster Macrocell clock to channel memory output clock in the same cluster Read and write minimum clock cycle time Data, read enable, and write enable set-up time relative to pin inputs Data, read enable, and write enable hold time relative to pin inputs Data access time to output pins from rising edge of read clock (read clock to data valid) Channel memory FIFO read clock to macrocell clock for read data Macrocell clock to channel memory FIFO write clock for write data 9.0 5.0 5.0 7.0 5.0 4.0 0.0 7.0 5.0 5.0 ns ns 10 5.0 3.3 0.0 11 7.5 9.0 6.0 2.0 1.0 6.0 0.5 9.0 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS Synchronous FIFO Data Parameters Document #: 38-02021 Rev. *B Page 28 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Channel Memory Timing Parameter Values (continued) Synchronous FIFO Flag Parameters tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA Read or write clock to respective flag output at output pins Read or write clock to macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset to Flag and Data Output Time Read/Write Clock Skew Time for Full Flag Read/Write Clock Skew Time for Empty Flag Read/Write Clock Skew Time for Boundary Flags Asynchronous channel memory access time from input of channel memory to output of channel memory 7.0 11 9 5.0 4.0 10.0 2.0 2.0 5.0 ns ns ns ns ns ns ns ns ns Internal Parameters High-Speed PSI Transceiver Timing Parameter Values Parameter Transceiver Interfacing Timing Parameters tTS tTXCLK tTXCLKD tTXCLKR tTXCLKF tTXDS tTXDH tRS tRXCLK tRXCLKD tRXCLKR tRXCLKF tRXDS tRXDH tRXPD TXCLK Frequency (must be frequency coherent to REFCLK) TXCLK Period TXCLK Duty Cycle TXCLK Rise Time TXCLK Fall Time Write Data Set-up to of TXCLK Write Data Hold from RXCLK Frequency RXCLK Period RXCLK Duty Cycle RXCLK Rise Time RXCLK Fall Time [11] [11] Description Min. 154.5 6.38 40 0.3 0.3 1.5 .5 154.5 6.38 43 0.1 0.1 2.2 2.2 -1.0 Max. 156.5 6.47 60 1.5 1.5 Unit MHz ns % ns ns ns ns of TXCLK 156.5 6.47 57 1.5 1.5 MHz ns % ns ns ns ns Recovered Data Set-up with regard to of RXCLK Recovered Data Hold with regard to of RXCLK Valid Propagation delay 1.0 ns Note: 11. For "slow slew rate" output delay adjustments, refer to Warp software's static timing analyzer results. Document #: 38-02021 Rev. *B Page 29 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY High-Speed PSI Transceiver Timing Parameter Values Parameter REFCLK Timing Parameters tREF tREFP tREFD tREFT tREFR tREFF tDRF tJD tJT tUID tRISE tFALL tTJ REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance (relative to received serial data) REFCLK Rise Time REFCLK Fall Time Driver Rise/Fall Time (20-80% rise, 80-20% fall, 100 balanced load) Deterministic Jitter Total Jitter Unit Interval CML Output Rise Time (20-80%, 100 balanced load) CML Output Fall Time (80-20%, 100 balanced load) Total Output Jitter (p-p) Total Output Jitter (rms) CML Serial Inputs (P25G01K100, P25G02K100 only) tEYE tJDR tJTR Eye opening Deterministic Jitter at Receiver Total Jitter at Receiver 140 0.41 0.65 ps UI UI 400 60 60 154.5 6.38 35 -100 0.3 0.3 100 0.17 0.35 400 170 170 0.05 0.007 156.5 6.47 65 +100 1.5 1.5 MHz ns % ppm ns ns ps UI UI ps ps ps UI UI Description Min. Max. Unit CML Serial Outputs (P25G01K100,P25G02K100 only) CML Serial Outputs (S25G01K100, S25G02K100 only) Transmit Interface Timing for High-Speed PSI tTXCLK tTXCLKDH tTXCLKDL TXCLK t TXDS tTXDH TXD[15:0] Document #: 38-02021 Rev. *B Page 30 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Receive Interface timing for High-Speed PSI tRXCLK tRXCLKDL tRXCLKDH RXCLK t RXPD t RXDS tRXDH RXD[15:0] Input & Output Standard Timing Delay Adjustments All the timing specifications in this data sheet are specified based on 3.3V PCI compliant inputs and outputs (fast slew rates[12]). Apply following adjustments if the inputs and outputs are configured to operate at other standards. Input/Output Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV Output Delay Adjustments tIOD 0.2 0.2 0.3 0.5 2.1 0 0.6[13] -0.3 -0.4 -0.1 -0.2 0.6 0.4 0.6 0.7 tEA 0 0 0.05 0.1 0.7 0 0.6[13] 0.3 0.2 0.4 0.2 0.9 0.8 0.5 0.6 tER 0 0 0 0 0.1 0 0.9[13] 0.1 0 0 0 0.5 0.5 0.1 0 Input Delay Adjustments tIOIN 0 0 0.1 0.2 0.5 0 0.5 0.5 0.5 0.9 0.9 0.5 0.5 0.5 0.5 tCKIN 0 0 0.1 0.2 0.4 0 0.4 0.3 0.3 0.5 0.5 0.5 0.5 0.5 0.5 tIOREGPIN 0 0 0.2 0.4 0.3 0 0.2 0.3 0.3 0.6 0.6 0.3 0.3 0.3 0.3 Notes: 12. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage. 13. RXCLK rise time and fall time are measured at the 20-80 percentile region of the rising and falling edge of the clock signal Document #: 38-02021 Rev. *B Page 31 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms General Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking (Macrocell) INPUT tMCS SYNCHRONOUS CLOCK tMCH REGISTERED OUTPUT tMCCO Registered Input in I/O Cell DATA INPUT tIOS tIOH INPUT REGISTER CLOCK tIOCO REGISTERED OUTPUT Document #: 38-02021 Rev. *B Page 32 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK tICS tSCS MACROCELL REGISTER CLOCK PT Clock to PT Clock DATA INPUT tMCSPT PT CLOCK tSCS2PT Asynchronous Reset/Preset RESET/PRESET INPUT tPRO REGISTERED OUTPUT tPRW tPRR CLOCK Output Enable/Disable GLOBAL CONTROL INPUT tER OUTPUTS tEA Document #: 38-02021 Rev. *B Page 33 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Cluster Memory Asynchronous Timing READ WRITE READ ADDRESS (AT THE CLUSTER INPUT) WRITE ENABLE tCLMPWE INPUT tCLMCLAA tCLMCLAA OUTPUT Cluster Memory Asynchronous Timing 2 READ ADDRESS (AT THE I/O PIN) tCLMSA tCLMHA WRITE READ WRITE ENABLE tCLMPWE INPUT tCLMSD tCLMAA tCLMHD tCLMAA OUTPUT Document #: 38-02021 Rev. *B Page 34 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Cluster Memory Synchronous Timing READ WRITE READ GLOBAL CLOCK tCLMS tCLMH tCLMCYC1 ADDRESS tCLMS tCLMH tCLMS tCLMH WRITE ENABLE REGISTERED INPUT tCLMDV1 tCLMDV1 tCLMDV1 REGISTERED OUTPUT Cluster Memory Internal Clocking MACROCELL INPUT CLOCK tCLMMACS1 tMACCLMS1 CLUSTER MEMORY INPUT CLOCK tCLMMACS2 tMACCLMS2 CLUSTER MEMORY OUTPUT CLOCK Document #: 38-02021 Rev. *B Page 35 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 EGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 REGISTERED OUTPUT Document #: 38-02021 Rev. *B Page 36 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory DP Asynchronous Timing ADDRESS An-1 An An+1 An+2 tCHMSA tCHMPWE tCHMHA WRITE ENABLE tCHMSD tCHMHD DATA INPUT Dn tCHMAA tCHMAA OUTPUT Dn-1 Dn Dn+1 Channel Memory Internal Clocking MACROCELL INPUT CLOCK tMACCHMS1 tCHMMACS1 CHANNEL MEMORY INPUT CLOCK tCHMMACS2 tMACCHMS2 CHANNEL MEMORY OUTPUT CLOCK Document #: 38-02021 Rev. *B Page 37 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK tMACCHMS FIFO WRITE CLOCK tCHMMACF FIFO READ OR WRITE CLOCK Channel Memory DP SRAM Flow Through R/W Timing CLOCK tCHMCYC1 tCHMS tCHMH ADDRESS An-1 An An+1 An+2 An+3 WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV1 tCHMDV1 tCHMDV1 tCHMDV1 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dn+3 Document #: 38-02021 Rev. *B Page 38 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing CLOCK tCHMCYC2 tCHMS tCHMH ADDRESS An-1 An tCHMH An+1 An+2 An+3 tCHMS WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV2 tCHMDV2 tCHMDV2 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dual-Port Asynchronous Address Match Busy Signal ADDRESS A Bn An ADDRESS B An-1 An An+1 tCHMBA tCHMBA ADDRESS MATCH Document #: 38-02021 Rev. *B Page 39 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Dual-Port Synchronous Address Match Busy Signal CLOCK ADDRESS A An-1 An ADDRESS B Bn-1 tCHMS An tCHMS Bn+1 ADDRESS MATCH tCHMBDV tCHMBDV Document #: 38-02021 Rev. *B Page 40 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory Synchronous FIFO Empty/Write Timing PORT B CLOCK tCHMCLK tCHMFS tCHMFH WRITE ENABLE REGISTERED INPUT Dn+1 EMPTY FLAG (active low) tCHMSKEW2 tCHMFO tCHMFO PORT A CLOCK READ ENABLE RE tCHMFRDV REGISTERED OUTPUT Document #: 38-02021 Rev. *B Page 41 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK tCHMCLK tCHMFS tCHMFH READ ENABLE tCHMFRDV REGISTERED OUTPUT FULL FLAG (active low) tCHMSKEW1 tCHMFO tCHMFO PORT B CLOCK WRITE ENABLE tCHMS tCHMH REGISTERED INPUT Document #: 38-02021 Rev. *B Page 42 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory Synchronous FIFO Programmable Flag Timing PORT B CLOCK tCHMCLK tCHMFH tCHMFS WRITE ENABLE PROGRAMMABLE ALMOST-EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO PORT A CLOCK tCHMFS READ ENABLE tCHMFH PORT B CLOCK tCHMCLK WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST-FULL FLAG (active LOW) tCHMSKEW3 tCHMFO PORT A CLOCK READ ENABLE Document #: 38-02021 Rev. *B Page 43 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Switching Waveforms (continued) Channel Memory Synchronous FIFO Master Reset Timing tCHMFRS MASTER RESET INPUT tCHMFRSR READ ENABLE / WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS tCHMFRSF HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS tCHMFRSF REGISTERED OUTPUT Document #: 38-02021 Rev. *B Page 44 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Limiting Amp High-Speed PSI 0.1 F Zo=50 IN+ IN- OUT+ OUT- 100 0.1 F Zo=50 Figure 17. Serial Input Termination. High-Speed PSI CY7B9532 Zo=50 100 Zo=50 0.1 F OUT+ OUT- 0.1 F Figure 18. Serial Output Termination. Document #: 38-02021 Rev. *B Page 45 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Pin and Signal Description Name CCLK Config_Done Data GCLK0-1 CCE GCTL0-3 IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 IO/VREF6 IO/VREF7 IO IO6/Lock MSEL Reconfig Reset TCLK TDI TDO TMS TXD[15:0] TXCLK RXD[15:0] Function Output Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Output Input Input Output Input Internal Internal Internal Signal Description Configuration Clock for serial interface with the external boot PROM Flag indicating that configuration is complete Pin to receive configuration data from the external boot PROM Global Input Clock signals 0 through 3 Chip select for the external boot PROM Global Control signals 0 through 3 Dual function pin: I/O or Reference Voltage for Bank 0 Dual function pin: I/O or Reference Voltage for Bank 1 Dual function pin: I/O or Reference Voltage for Bank 2 Dual function pin: I/O or Reference Voltage for Bank 3 Dual function pin: I/O or Reference Voltage for Bank 4 Dual function pin: I/O or Reference Voltage for Bank 5 Dual function pin: I/O or Reference Voltage for Bank 6 Dual function pin: I/O or Reference Voltage for Bank 7 Input or Output pin Dual function pin: I/O in Bank 6 or PLL lock output signal Mode Select Pin Pin to start configuration of PSI Reset signal to interface with the external boot PROM JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLK. TXD[15] is the most significant bit (the first bit transmitted) Parallel Transmit Data Input Clock. Divide by 16 of the selected transmit bit-rate clock Parallel Receive Data Output. These outputs change following RXCLK. RXD[15] is the most significant bit of the output word, and is received first on the serial interface Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial stream Common Mode Termination. Capacitor shunt to VSS for common mode noise Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive) Standard Device Signals Transmit Path Signals Receive Path Signals RXCLK CM_SER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK Internal Analog Analog Analog Analog Analog Transceiver Control and Status Signals Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and input receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel interface Internal Line Fault Indicator Output Signal. When LOW, this signal indicates that the selected receive data stream has been detected as invalid by either a LOW input on SD, or by the receive VCO being operated outside its specified limits LFI Document #: 38-02021 Rev. *B Page 46 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Pin and Signal Description (continued) Name RESET LOCKREF SD FIFO_ERR FIFO_RST PWRDN Function Internal Internal LVTTL input Internal Internal Internal Signal Description Reset for all logic functions except the transmit FIFO Receive PLL Lock to Reference Input Signal. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream Transmit FIFO Error Output Signal. When HIGH the transmit FIFO has either under or overflowed. The FIFO must be reset to clear the error indication Transmit FIFO Reset Input Signal. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation Device Power Down Input Signal. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated Diagnostic Loopback Control Input Signal. When HIGH, transmit data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs Line Loopback Control Input Signal. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT line driver is generated in the transmit shifter Analog Line Loopback Input Signal. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT line driver is controlled by LINELOOP Loop Time Mode Input Signal. When HIGH, the extracted receive bit-clock replaces transmit bit-clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50 transmission lines or commercial fiberoptic transmitter modules Differential Serial Data Input. This differential input accept the serial data stream for deserialization and clock extraction +3.3V Supply (operating voltage) Signal and Power Ground +3.3V Quiet Power Quiet Ground +1.5V Supply for HSTL Outputs Power Power Power Power Power Power Power Power Power Power VCC for I/O bank 0 VCC for I/O bank 1 VCC for I/O bank 2 VCC for I/O bank 3 VCC for I/O bank 4 VCC for I/O bank 5 VCC for I/O bank 6 VCC for I/O bank 7 VCC for JTAG pins VCC for Configuration port Page 47 of 58 Transceiver Loop Control Signals DIAGLOOP Internal LINELOOP Internal LOOPA Internal LOOPTIME Internal Serial I/O OUT (OUTP/OUTN) IN Power VCC GND VCCQ VSSQ VDDQ VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJTAG VCCCNFG Power Ground Differential CML output Differential CML input Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY Pin and Signal Description (continued) Name VCCPLL VCEP Function Power Power VCC for logic PLL VCC for the Self-BootTM solution embedded boot PROM Signal Description Pin Configurations 456-Ball BGA (25G01K100) Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF GND 2 HSTLREF 3 IO7 4 IO7 5 IO7 6 IO7 7 HSTLREF IO7 8 IO7 9 IO7 10 IO7 11 HSTLREF IO6 12 HSTLREF IO6 13 IO6 14 IO6 15 IO6 16 HSTLREF IO6 17 IO5 18 IO5 19 IO5 20 IO/VRE F5 IO5 21 IO5 22 IO5 23 IO5 24 IO/VRE F5 IO5 25 IO5 26 GND A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF HSTL- HSTLREF REF IO0 IO7 IO7 HSTLREF IO7 IO7 IO7 VDDQ IO7 HSTLREF IO7 IO6 IO6 IO6 IO5 IO5 IO5 IO5 IO/VRE F5 IO5 IO5 IO5 IO5 IO7 VDDQ VCC VCCVC C VDDQ IO7 GCTL3 VDDQ VDDQ VDDQ HSTLREF IO6 IO6 IO6 IO5 IO5 IO5 GCTL2 GCTL1 IO5 IO5 TDO TCK IO0 IO0 IO0 IO7 VDDQ VDDQ GND HSTLREF GND IO7 NC VDDQ VCC IO6 IO6 VCPLL VDDQ VDDQ VDDQ VCC NC GCLK1 IO5 TMS TDI IO0 IO0 IO0 GCTL0 GND GND IO7 GND HSTLREF IO6 IO6 IO6 IOP6 IO6 IO6 IO/VRE F5 IO5 IO5 IO5 IO5 IO5 VCCO5 VCCO5 VCCO5 VCJTG IO/VRE F0 IO0 IO0 IO0 VCC GND NC NC NC NC NC IO/VRE F0 IO0 VCC VCCO0 GCLK0 NC NC NC NC NC IO0 VCC VCCO0 GND NC VSSQ VSSQ NC NC IO0 IO0 VCC VCCO0 GND NC VSSQ VSSQ VSSQ NC IO0 IO0 IO0 IO0 VCC VSSQ VSSQ VSSQ NC NC IO0 IO0 IO0 GND IO0 GND GND GND GND GND GNPLL NC NC NC NC NC IO0 IO/VRE F0 IO0 IO0 GND IO0 GND GND GND GND GND GND SD RXCN1 RXCP1 RXCN2 RXCP2 VCC IO0 GND IO/VRE F0 IO0 GND GND GND GND GND GND NC VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO1 IO1 GND GND GND GND GND GND NC VSSQ VSSQ INP INN IO1 IO1 IO1 VCCO1 GND GND GND GND GND GND GND NC VSSQ VSSQ VSSQ CMSER IO/VRE IO/VRE F1 F1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND GND GND VSSQ VSSQ VSSQ OUTP OUTN IO1 GND GND NC VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO/VRE F1 IO1 IO1 GND REF- VCCO4 CLKP REF- VCCO4 CLKN IO4 VCEP IO4 IO4 VCCO4 IO1 IO1 IO1 GND IO4 IO4 IO4 IO1 IO1 VCEP IO1 IO1 IO4 IO4 IO/VRE F4 IO4 IO1 IO1 VCCO1 IO/VRE F1 IO1 GND IO4 NC IO4 IO4 GND CDONE VCCO1 IO2 GND GND GND IO2 IO/VRE F2 NC IO2 IO2 IO3 IO3 GND IO3 GND GND GND IO3 IO3 IO3 IO4 IO4 IO4 IO4 CDATA RECON FIG CRST CCLK IO2 IO2 VCCFG VCCO2 VCCO2 VCCO2 VCCO2 IO2 IO2 IO2 VDDQ VCCO3 VCCO3 IO3 IO3 IO/VRE F3 IO3 NC NC VCCO4 IO/VRE IO/VRE F4 F4 IO3 IO4 IO4 IO2 IO2 IO2 IO2 IO2 NC VDDQ VDDQ IO2 IO2 IO/VRE F2 IO2 IO2 IO3 IO3 IO3 IO3 VCC VCCO3 VCCO3 IO/VRE F3 IO/VRE F3 IO3 IO3 IO3 IO3 IO3 CCE MSEL IO/VRE F2 IO2 IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VRE F3 IO3 IO3 GND IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 VCC IO/VRE F3 IO3 IO3 IO/VRE F3 IO3 IO3 IO3 IO3 IO3 IO3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Document #: 38-02021 Rev. *B Page 48 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA (25G02K100) Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF GND 2 IO/ VREF7 3 NC 4 NC 5 NC 6 NC 7 IO/ VREF7 NC 8 NC 9 NC 10 IO7 11 12 13 NC 14 NC 15 NC 16 IO/ VREF6 NC 17 IO5 18 IO5 19 IO5 20 IO/VRE F5 IO5 21 IO5 22 IO5 23 IO5 24 IO/VRE F5 IO5 25 IO5 26 GND IO/ IO/ VREF6 VREF6 NC NC A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF IO/ IO/ VREF7 VREF7 IO0 NC NC IO/ VREF7 NC NC NC VDDQ IO7 IO/ VREF6 IO7 IO6 NC NC IO5 IO5 IO5 IO5 IO/VRE F5 IO5 IO5 IO5 IO5 NC VDDQ VCC VCC NC GCTL3 VDDQ VDDQ VDDQ IO/ VREF6 NC NC NC IO5 IO5 IO5 GCTL2 GCTL1 IO5 IO5 TDO TCK IO0 IO0 IO0 NC VDDQ VDDQ VDDQ GND IO/ VREF7 GND IO7 VCC VDDQ VCC NC IO6 VCPLL VDDQ VDDQ VDDQ VCC VDDQ NC IO5 TMS TDI IO0 IO0 IO0 GCTL0 GND GND NC GNDO IO/ VREF6 NC NC NC IOP6 NC IO6 IO/VRE F5 IO5 IO5 IO5 IO5 IO5 VCCO5 VCCO5 VCCO5 VCJTG IO/VRE F0 IO0 IO0 IO0 VCC GND SD_B RXCP2 RXCN2 RXCP1 RXCN1 _B _B _B _B VDDQ VCCQ VCCQ VCCQ VCCQ IO/VRE F0 IO0 VCC VCCO0 GCLK0 IO0 VCC VCCO0 GND NC VSSQ VSSQ INP_B INN_B IO0 IO0 VCC VCCO0 GND NC VSSQ VSSQ VSSQ CMSER _B IO0 IO0 IO0 IO0 VCC VSSQ VSSQ VSSQ OUTN_ OUTP_ B B VCCQ VCCQ VCCQ IO0 IO0 IO0 GND IO0 GND GND GND GND GND GNPLL VDDQ VCCQ IO0 IO/VRE F0 IO0 IO0 GND IO0 GND GND GND GND GND GND SD RXCN1 RXCP1 RXCN2 RXCP2 VCC IO0 GND IO/VRE F0 IO0 GND GND GND GND GND GND VDDQ VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO1 IO1 GND GND GND GND GND GND NC VSSQ VSSQ INP INN IO1 IO1 IO1 VCCO1 GNDO GND GND GND GND GND GND NC VSSQ VSSQ VSSQ CMSER IO/VRE IO/VRE F1 F1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND GND GND VSSQ VSSQ VSSQ OUTP OUTN IO1 GND GND VDDQ VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO/VRE F1 IO1 IO1 GND REF- VCCO4 CLKP REF- VCCO4 CLKN IO4 VCEP IO4 IO4 VCCO4 IO1 IO1 IO1 GND IO4 NC NC IO1 IO1 VCEP IO1 IO1 IO4 NC NC IO1 IO1 VCCO1 IO/VRE GNDO F1 IO1 IO2 GND GND GND IO2 IO/VRE F2 VCC IO2 IO2 IO3 IO3 GND IO3 GND GND GND IO3 IO3 IO4 VCC IO4 NC NC GND CDONE VCCO1 IO3 IO4 IO4 NC NC CDATA RECON FIG CRST CCLK IO2 IO2 VCCFG VCCO2 VCCO2 VCCO2 VCCO2 IO2 IO2 IO2 VDDQ VCCO3 VCCO3 IO3 IO3 IO/VRE F3 IO3 VCC VDDQ VCCO4 IO/VRE IO/VRE F4 F4 VCCO3 VCCO3 IO/VRE F3 IO/VRE F3 IO3 IO3 IO3 IO3 NC NC IO2 IO2 IO2 IO2 IO2 VCC VDDQ VDDQ IO2 IO2 IO/VRE F2 IO2 IO2 IO3 IO3 IO3 IO3 VCC IO3 IO3 CCE MSEL IO/VRE F2 IO2 IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO/ VREF3 IO3 IO3 GND IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 VCC IO/VRE F3 IO3 IO3 IO/VRE F3 IO3 IO3 IO3 IO3 IO3 IO3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Document #: 38-02021 Rev. *B Page 49 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) 456-Ball BGA Pin Table Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 25G01K100 GND HSTLREF IO7 IO7 IO7 IO7 HSTLREF IO7 IO7 IO7 HSTLREF HSTLREF IO6 IO6 IO6 HSTLREF IO5 IO5 IO5 IO/VREF5 IO5 IO5 IO5 IO/VREF5 IO5 GND HSTLREF HSTLREF IO7 HSTLREF IO7 IO7 IO7 VDDQ IO7 HSTLREF IO6 IO6 IO6 IO6 25G02K100 GND IO/VREF7 NC NC NC NC IO/VREF7 NC NC IO7 IO/VREF6 IO/VREF6 NC NC NC IO/VREF6 IO5 IO5 IO5 IO/VREF5 IO5 IO5 IO5 IO/VREF5 IO5 GND IO/VREF7 IO/VREF7 NC IO/VREF7 NC NC NC VDDQ IO7 IO/VREF6 NC NC IO6 NC Pin B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 25G01K100 IO6 IO6 IO5 IO5 IO5 IO5 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO0 IO7 IO7 IO7 VDDQ VCC VCC IO7 GCTL3 IO7 VDDQ VDDQ VDDQ HSTLREF IO6 IO6 IO5 IO5 IO5 GCTL2 GCTL1 IO5 IO5 IO5 TDO TCK IO0 IO0 IO0 25G02K100 NC NC IO5 IO5 IO5 IO5 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO0 NC NC NC VDDQ VCC VCC NC GCTL3 IO7 VDDQ VDDQ VDDQ IO/VREF6 NC NC IO5 IO5 IO5 GCTL2 GCTL1 IO5 IO5 IO5 TDO TCK IO0 IO0 IO0 Page 50 of 58 Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) Pin D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 25G01K100 IO7 VDDQ VDDQ VDDQ GND HSTLREF IO7 NC VDDQ VCC IO6 IO6 IO6 VCPLL VDDQ VDDQ VDDQ VCC NC GCLK1 IO5 TMS TDI IO0 IO0 IO0 GCTL0 GND GND IO7 GND GND HSTLREF IO6 IO6 IO6 IOP6 IO6 IO6 IO/VREF5 IO5 25G02K100 NC VDDQ VDDQ VDDQ GND IO/VREF7 IO7 VCC VDDQ VCC NC NC IO6 VCPLL VDDQ VDDQ VDDQ VCC VDDQ NC IO5 TMS TDI IO0 IO0 IO0 GCTL0 GND GND NC GNDO GND IO/VREF6 NC NC NC IOP6 NC IO6 IO/VREF5 IO5 456-Ball BGA Pin Table (continued) Pin E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 25G01K100 IO5 IO5 IO5 IO5 VCCO5 VCCO5 VCCO5 VCJTG IO/VREF0 IO0 IO0 VCC GND NC NC NC NC NC IO0 IO/VREF0 VCC VCCO0 GCLK0 NC NC NC NC NC IO0 IO0 VCC VCCO0 GND NC VSSQ VSSQ NC NC IO0 IO0 VCC 25G02K100 IO5 IO5 IO5 IO5 VCCO5 VCCO5 VCCO5 VCJTG IO/VREF0 IO0 IO0 VCC GND SD_B RXCP2_B RXCN2_B RXCP1_B RXCN1_B IO0 IO/VREF0 VCC VCCO0 GCLK0 VDDQ VCCQ VCCQ VCCQ VCCQ IO0 IO0 VCC VCCO0 GND NC VSSQ VSSQ INP_B INN_B IO0 IO0 VCC Page 51 of 58 Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) Pin J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 25G01K100 VCCO0 GND NC VSSQ VSSQ VSSQ NC IO0 IO0 IO0 IO0 VCC VSSQ VSSQ VSSQ NC NC IO0 IO0 IO0 GND IO0 GND GND GND GND GND GNPLL NC NC NC NC NC IO0 IO/VREF0 IO0 GND IO0 GND GND GND 25G02K100 VCCO0 GND NC VSSQ VSSQ VSSQ CMSER_B IO0 IO0 IO0 IO0 VCC VSSQ VSSQ VSSQ OUTN_B OUTP_B IO0 IO0 IO0 GND IO0 GND GND GND GND GND GNPLL VDDQ VCCQ VCCQ VCCQ VCCQ IO0 IO/VREF0 IO0 GND IO0 GND GND GND 456-Ball BGA Pin Table (continued) Pin M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 25G01K100 GND GND GND SD RXCN1 RXCP1 RXCN2 RXCP2 VCC IO0 IO0 GND IO/VREF0 GND GND GND GND GND GND NC VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO1 IO1 IO0 GND GND GND GND GND GND NC VSSQ VSSQ INP INN IO1 25G02K100 GND GND GND SD RXCN1 RXCP1 RXCN2 RXCP2 VCC IO0 IO0 GND IO/VREF0 GND GND GND GND GND GND VDDQ VCCQ VCCQ VCCQ VCCQ IO1 IO1 IO1 IO1 IO0 GND GND GND GND GND GND NC VSSQ VSSQ INP INN IO1 Page 52 of 58 Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) Pin R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 25G01K100 IO1 IO1 VCCO1 GND GND GND GND GND GND GND NC VSSQ VSSQ VSSQ CMSER IO/VREF1 IO/VREF1 IO1 IO1 IO1 GND GND GND GND GND GND VSSQ VSSQ VSSQ OUTP OUTN IO1 IO1 IO1 GND GND NC VCCQ VCCQ VCCQ VCCQ 25G02K100 IO1 IO1 VCCO1 GNDO GND GND GND GND GND GND NC VSSQ VSSQ VSSQ CMSER IO/VREF1 IO/VREF1 IO1 IO1 IO1 GND GND GND GND GND GND VSSQ VSSQ VSSQ OUTP OUTN IO1 IO1 IO1 GND GND VDDQ VCCQ VCCQ VCCQ VCCQ 456-Ball BGA Pin Table (continued) Pin V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 25G01K100 IO1 IO1 IO/VREF1 IO1 GND REFCLKP VCCO4 IO4 IO4 VCCO4 IO1 IO1 IO1 IO1 GND REFCLKN VCCO4 IO4 IO4 IO4 IO1 IO1 VCEP IO1 IO1 IO4 VCEP IO4 IO4 IO/VREF4 IO1 IO1 VCCO1 IO/VREF1 GND IO4 NC IO4 IO4 IO4 GND 25G02K100 IO1 IO1 IO/VREF1 IO1 GND REFCLKP VCCO4 IO4 IO$ VCCO4 IO1 IO1 IO1 IO1 GND REFCLKN VCCO4 IO4 IO4 IO4 IO1 IO1 VCEP IO1 IO1 IO4 VCEP IO4 IO1 IO1 IO1 IO1 VCCO1 IO/VREF1 GNDO IO4 VCC IO4 NC NC GND Page 53 of 58 Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) Pin AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 25G01K100 CDONE VCCO1 IO1 IO2 GND GND GND IO2 IO/VREF2 IO2 IO2 IO3 IO3 GND IO3 GND GND GND IO3 IO3 IO3 IO4 IO4 IO4 IO4 CDATA RECONFIG IO2 IO2 VCCFG VCCO2 VCCO2 VCCO2 VCCO2 NC IO2 IO2 IO2 VDDQ VCCO3 VCCO3 25G02K100 CDONE VCCO1 IO1 IO2 GND GND GND IO2 IO/VREF2 IO2 IO2 IO3 IO3 GND IO3 GND GND GND IO3 IO3 IO3 IO4 IO4 NC NC CDATA RECONFIG IO2 IO2 VCCFG VCCO2 VCCO2 VCCO2 VCCO2 VCC IO2 IO2 IO2 VDDQ VCCO3 VCCO3 456-Ball BGA Pin Table (continued) Pin AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 25G01K100 IO3 IO3 IO/VREF3 NC NC VCCO4 IO/VREF4 IO/VREF4 IO4 IO4 CRST CCLK IO2 IO2 IO2 IO2 IO2 NC VDDQ VDDQ IO2 IO2 IO/VREF2 IO2 IO3 IO3 IO3 IO3 IO3 VCC VCCO3 VCCO3 IO/VREF3 IO3 IO3 IO3 CCE MSEL IO/VREF2 IO2 IO/VREF2 25G02K100 IO3 IO3 IO/VREF3 VCC VDDQ VCCO4 IO/VREF4 IO/VREF4 NC NC CRST CCLK IO2 IO2 IO2 IO2 IO2 VCC VDDQ VDDQ IO2 IO2 IO/VREF2 IO2 IO3 IO3 IO3 IO3 IO3 VCC VCCO3 VCCO3 IO/VREF3 IO3 IO3 IO3 CCE MSEL IO/VREF2 IO2 IO/VREF2 Page 54 of 58 Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY 456-Ball BGA Pin Table (continued) Pin AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 25G01K100 IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 IO/VREF3 IO3 GND IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 VCC IO/VREF3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 25G02K100 IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 IO/VREF3 IO3 GND IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 VCC IO/VREF3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 Page 55 of 58 456-Ball BGA Pin Table (continued) Pin AF21 AF22 AF23 AF24 AF25 AF26 25G01K100 IO3 IO3 IO3 IO3 IO3 GND 25G02K100 IO3 IO3 IO3 IO3 IO3 GND Document #: 38-02021 Rev. *B Programmable Serial Interface (High Speed Devices) PRELIMINARY CY P 25G 02 K200 V 1 - MG C Standard Cypress Designator P = PHY S = SONET PHY 15 = 1.5Gbps 25 = 2.5Gbps 32 = 3.2Gbps 100 = 10.0Gbps C = Commercial I = Industrial MG = Multichip BGA 1 = 456 ball 2 = 700 ball X = TBD 01 = 1 channel 02 = 2 channel 04 = 4 channel 08 = 8 channel 12 = 12 channel V = Standard Power 3.3V-Vcc L = Low Power Mixed 2.5V & 3.3V-Vcc K100 = 100K gates K200 = 200K gates Ordering Information Device 25G01K100 25G02K100 15G04K100 15G04K200 15G08K200 Channels & Link Speed 1 x 2.5 Gbps 1 x 2.5 Gbps 2 x 2.5 Gbps 2 x 2.5 Gbps Ordering Code CYP25G01K100V1-MGC CYS25G01K100V1-MGC CYP25G02K100V1-MGC CYS25G02K100V1-MGC Package Name 456MGC 456MGC 456MGC 456MGC 456MGC 700MGC 700MGC Package Type 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 700-Ball Ball Grid Array 700-Ball Ball Grid Array Commercial Industrial Commercial Operating Range Commercial 4 x 0.2 - 1.5 Gbps CYP15G04K100V1-MGC 4 x 0.2 - 1.5 Gbps CYP15G04K200V2-MGC 8 x 0.2 - 1.5 Gbps CYP15G08K200V2-MGC Document #: 38-02021 Rev. *B Page 56 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY Package Diagrams 456-Lead Ball Grid Array (35 x 35 x 2.33 mm) BG456 51-85133 NoBL, Programmable Interconnect Matrix, PIM, Spread Aware, Warp, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, Programmable Serial Interface, and PSI are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of IDT. InfiniBand is a trademark of the InfiniBand Trade Association. QDR is a trademark of Micron, IDT, and Cypress Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. SpeedWave, and ViewDraw are trademarks of ViewLogic. Document #: 38-02021 Rev. *B Page 57 of 58 Programmable Serial Interface (High Speed Devices) PRELIMINARY ac Document Title: Programmable Serial Interface Device Family (High Speed) Programmable Bandwidth Document Number: 38-02021 REV. ** *A *B ECN NO. 106745 107726 109064 Issue Date 05/25/01 06/04/01 09/07/01 Orig. of Change SZV MHW MHW Description of Change Change from Spec #38-01093 to 38-02021 Updated Marketing Part Numbers Added x8 feature in PLL and CHAR data Document #: 38-02021 Rev. *B Page 58 of 58 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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